Semiconductor memory devices, memory systems including the same and methods of operating the same

ABSTRACT

A semiconductor memory device includes a memory cell array, a control logic circuit, an internal processing circuit, and an error correction circuit. The control logic circuit generates an internal processing mode signal in response to a command from a memory controller. The internal processing circuit selectively performs the internal processing operation on a first set of data read from the memory cell array to output a processing result data, in response to the internal processing mode signal. The error correction circuit performs an error correction code (ECC) encoding on the processing result data to generate a second parity data and stores the processing result data and the second parity data in the memory cell array. The error correction circuit generates the second parity data by selecting the same ECC of a plurality of ECCs as a first ECC.

CROSS-REFERENCE TO RELATED APPLICATIONS

This US application claims the benefit of priority under 35 USC § 119 toKorean Patent Application No. 10-2016-0103992, filed on Aug. 17, 2016,in the Korean Intellectual Property Office, the content of which isincorporated herein in its entirety by reference.

BACKGROUND

The present disclosure relates to memories, and more particularly tosemiconductor memory devices, memory systems including the same andmethods of operating the same.

Semiconductor memory devices may be classified into non-volatile memorydevices such as flash memory devices and volatile memory devices such asDRAMs. High speed operation and cost efficiency of DRAMs make itpossible for DRAMs to be used for system memories. However, due to thecontinuing shrinking in fabrication design rules of DRAMs, bit errors ofmemory cells in the DRAMs may rapidly increase.

SUMMARY

Some exemplary embodiments may provide a semiconductor memory device,capable of enhancing performance.

Some exemplary embodiments may provide a memory system including thesemiconductor memory device.

Some exemplary embodiments may provide method of operating asemiconductor memory device, capable of enhancing performance

According to exemplary embodiments, a semiconductor memory deviceincludes a memory cell array, a control logic circuit, an internalprocessing circuit and an error correction circuit. The memory cellarray includes a plurality of memory cells coupled to a plurality ofword-lines and a plurality of bit-lines. The control logic circuitgenerates an internal processing mode signal designating whether toperform an internal processing operation in response to a commandreceived from a memory controller. The internal processing circuitoutputs a processing result data by selectively performing the internalprocessing operation on a first set of data read from the memory cellarray, in response to the internal processing mode signal. The errorcorrection circuit generates a second parity data by performing an errorcorrection code (ECC) encoding on the processing result data and storesthe processing result data and the second parity data in the memory cellarray. The error correction circuit generates the second parity data byselecting the same ECC of a plurality of ECCs as a first ECC which isused for generating a first parity data of the first set of data.

According to exemplary embodiments, a memory system includes at leastone semiconductor memory device and a memory controller. The memorycontroller controls the at least one semiconductor memory device. Thememory controller generates a first parity data by performing an errorcorrection code (ECC) encoding on a write data using a first ECC andtransmits the write data and the first parity data to the at least onesemiconductor memory device. The at least one semiconductor memorydevice includes memory cell array, a control logic circuit, an internalprocessing circuit and a first error correction circuit. The memory cellarray includes a plurality of memory cells coupled to a plurality ofword-lines and a plurality of bit-lines and stores the write data andthe first parity data. The control logic circuit generates an internalprocessing mode signal designating whether to perform an internalprocessing operation in response to a command from the memorycontroller. The internal processing circuit outputs a processing resultdata by selectively performing the internal processing operation on afirst set of data including the write data and the first parity data, inresponse to the internal processing mode signal. The first errorcorrection circuit generates a second parity data by performing an ECCencoding on the processing result data and stores the processing resultdata and the second parity data in the memory cell array. The firsterror correction circuit generates the second parity data by selectingthe same ECC of a plurality of ECCs as the first ECC which the memorycontroller uses for generating the first parity data.

According to exemplary embodiments, in a method of operating asemiconductor memory device comprising a memory cell array including aplurality of memory cells coupled to a plurality of word-lines and aplurality of bit-lines, and a control logic circuit to control access tothe memory cell array, a command from a memory controller is received bythe control logic circuit to perform an internal processing operation ona first set of data stored in the memory cell array, the internalprocessing operation is performed on the first set of data, by aninternal processing circuit of the semiconductor memory device, toprovide a processing result data to an error correction circuit, aparity data is generated by the error correction circuit based on theprocessing result data, the processing result data and the parity dataare stored in a target page of the memory cell array and processingresult data and the parity data are transmitted to the memorycontroller.

According to exemplary embodiments, a semiconductor memory deviceincludes memory cell array, an error correction circuit, and an internalprocessing circuit. The error correction circuit is configured togenerate a corrected data by performing an error correction on a readdata from the memory cell array, the read data including a first maindata and a first parity data. The internal processing circuit isconfigured to generate a first processed data by performing an internalprocessing on the corrected data including a second main data and asecond parity data. The error correction circuit is further configuredto generate a third parity data by performing an error correction on thefirst processed data, and store the third parity data and the firstprocessed data in the memory cell array.

Accordingly, the semiconductor memory device according to exemplaryembodiments supports in-memory processing and may greatly reducetransmission through memory-controller interface. Therefore, exemplaryembodiments may save memory bandwidth and increase usability of thesemiconductor memory device by generating a second parity data using thesame ECC of the ECCs as a first ECC in the memory controller.

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments will be described below in more detail withreference to the accompanying drawings.

FIG. 1 is a block diagram illustrating an electronic system according toexemplary embodiments.

FIG. 2 is a block diagram illustrating the memory system shown in FIG. 1according to example embodiments.

FIG. 3 is a block diagram illustrating the semiconductor memory deviceshown in FIG. 2, according to exemplary embodiments.

FIGS. 4A to 4E are circuit diagrams of examples of a memory cell shownin FIG. 3, according to exemplary embodiments.

FIG. 5 illustrates an example of a memory cell (referred to as STT-MRAMcell) shown in FIG. 3, according to exemplary embodiments.

FIG. 6A illustrates a portion of the semiconductor memory device of FIG.3 in a non-internal processing mode (a normal mode) according toexemplary embodiments.

FIG. 6B illustrates a portion of the semiconductor memory device of FIG.3 in a non-internal processing mode (a normal mode) according to otherexemplary embodiments.

FIG. 7A illustrates a portion of the semiconductor memory device of FIG.3 in an internal processing mode according to exemplary embodiments.

FIG. 7B illustrates a portion of the semiconductor memory device of FIG.3 in an internal processing mode according to other exemplaryembodiments.

FIG. 8 illustrates the second error correction circuit shown in FIG. 3according to exemplary embodiments.

FIG. 9 illustrates an ECC engine in the second error correction circuitof FIG. 8 according to exemplary embodiments.

FIG. 10 is a diagram illustrating a memory system according to exemplaryembodiments.

FIG. 11 is a diagram illustrating an example of a high bandwidth memory(HBM) organization.

FIG. 12 is a structural diagram illustrating a semiconductor memorydevice according to exemplary embodiments.

FIG. 13 is a flow chart illustrating a method of operating asemiconductor memory device according to exemplary embodiments.

FIG. 14 is a flow chart illustrating in-memory processing of a pop-countoperation in a method of FIG. 13 according to exemplary embodiments.

FIG. 15 is a flow chart illustrating a method of operating asemiconductor memory device according to exemplary embodiments.

FIG. 16 illustrates that a logical bitwise operation is performed in thesemiconductor memory device of FIG. 3 according to exemplaryembodiments.

FIG. 17 is a flow chart illustrating a method of operating a memorysystem according to exemplary embodiments.

FIG. 18 is a cross-sectional view illustrating a package structureincluding the semiconductor memory device according to exemplaryembodiments.

FIG. 19 is a block diagram illustrating a mobile system including thesemiconductor memory device according to exemplary embodiments.

DETAILED DESCRIPTION

Various exemplary embodiments will be described more fully hereinafterwith reference to the accompanying drawings, in which some exemplaryembodiments are shown.

It will be understood that, although the terms first, second, third etc.may be used herein to describe various elements, these elements shouldnot be limited by these terms. Unless indicated otherwise, these termsare generally used to distinguish one element from another. Thus, afirst element discussed below in one section of the specification couldbe termed a second element in a different section of the specificationwithout departing from the teachings of the present disclosure. Also,terms such as “first” and “second” may be used in the claims to name anelement of the claim, even thought that particular name is not used todescribe in connection with the element in the specification. As usedherein, the term “and/or” includes any and all combinations of one ormore of the associated listed items. Expressions such as “at least oneof,” when preceding a list of elements, modify the entire list ofelements and do not modify the individual elements of the list.

FIG. 1 is a block diagram illustrating an electronic system according toexemplary embodiments.

As used herein, a semiconductor memory device or a memory device mayrefer, for example, to a device such as a semiconductor chip (e.g.,memory chip and/or logic chip formed from a wafer), a stack ofsemiconductor chips, a semiconductor package including one or moresemiconductor chips stacked on a package substrate, or apackage-on-package device including a plurality of packages.

An electronic system, as used herein, may refer to one of these devicesand may also include products that include these devices, such as amemory card, a memory module, a hard drive including additionalcomponents, a mobile phone, laptop, tablet, desktop, camera, server,computing system, or other consumer electronic device, etc.

Referring to FIG. 1, an electronic system 10 may include a host 15 and amemory system 20. The memory system 20 may include a memory controller100 and a plurality of semiconductor memory devices 200 a˜200 n (n is aninteger greater than two).

The host 15 may communicate with the memory system 20 through variousinterface protocols such as Peripheral Component Interconnect-Express(PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA),Parallel ATA (PATA), or serial attached SCSI (SAS). In addition, thehost 15 may also communicate with the memory system 20 through interfaceprotocols such as Universal Serial Bus (USB), Multi-Media Card (MMC),Enhanced Small Disk Interface (ESDI), or Integrated Drive Electronics(IDE).

The memory controller 100 may control an overall operation of the memorysystem 20. The memory controller 100 may control an overall dataexchange between the host 15 and the plurality of semiconductor memorydevices 200 a˜200 n. For example, the memory controller 100 may writedata in the plurality of semiconductor memory devices 200 a˜200 n orread data from the plurality of semiconductor memory devices 200 a˜200 nin response to request from the host 15.

In addition, the memory controller 100 may issue operation commands tothe plurality of semiconductor memory devices 200 a˜200 n forcontrolling the plurality of semiconductor memory devices 200 a˜200 n.

In some embodiments, each of the plurality of semiconductor memorydevices 200 a˜200 n may be a may be a memory device including resistivetype memory cells such as a magnetoresistive random access memory(MRAM), a resistive random access memory (RRAM), a phase change randomaccess memory (PRAM) and a ferroelectric random access memory (FRAM),etc. In other exemplary embodiments, each of the plurality ofsemiconductor memory devices 200 a˜200 n may be a memory deviceincluding dynamic memory cells such as a dynamic random access memory(DRAM).

An MRAM is a nonvolatile memory device based on magnetoresistance. AnMRAM is different from a volatile RAM in many aspects. For example,since an MRAM is nonvolatile, the MRAM may retain all stored data evenwhen power is turned off.

Although a nonvolatile RAM is generally slower than a volatile RAM, anMRAM has read and write response times comparable with read and writeresponse times of a volatile RAM. Unlike a conventional RAM that storesdata as electric charge, an MRAM stores data by using magnetoresistance(or magnetoresistive) elements. In general, a magnetoresistance elementis made of two magnetic layers, each having a magnetization.

FIG. 2 is a block diagram illustrating the memory system shown in FIG. 1according to example embodiments.

In FIG. 2, only one semiconductor memory device 200 a in communicationwith the memory controller 100 is illustrated for convenience. However,the details discussed herein related to semiconductor memory device 200a may equally apply to the other semiconductor memory devices 200 b˜200n.

Referring to FIG. 2, the memory system 20 may include the memorycontroller 100 and the semiconductor memory device 200 a. The memorycontroller 20 transmits a command CMD and an address ADDR to thesemiconductor memory device 200 a. The memory controller 20 exchanges amain data MD and a parity data PRT with the semiconductor memory device200 a through a main data line and a parity data line. In one exampleembodiment, the main data MD and the parity data PRT may be transmittedthrough a common data line (e.g., DQ). The parity data PRT may begenerated based on the main data MD and may be used for correctingerrors of the main data MD.

When the memory controller 100 transmits the main data MD to thesemiconductor memory device 200 a, a first error correction circuit 110in the memory controller 100 may generate the parity data PRT using afirst error correction code (ECC1) 120. The first error correction code120 may be at least one of a single error correction (SEC) code, asingle error correction and double error detection (SECDED) code, anddouble error correction (DEC) code.

The semiconductor memory device 200 a may include a memory cell array300 in which the main data MD and the parity data PRT are stored and acontrol logic circuit 210 which controls an access to the memory cellarray 300. The semiconductor memory device 200 a may further include aninternal processing circuit (the internal processing circuit may be alsoreferred to as a processing in-memory circuit (PIMC)) 390 and a seconderror correction circuit 400. The internal processing circuit 390 may beselectively enabled when the command CMD directs an internal processingoperation, and the internal processing circuit 390 performs an internalprocessing on a first set of data (hereinafter, may be referred to as abit vector) stored in the memory cell array 300 to generate anprocessing result data indicating a result of the internal processingoperation. The first set of data stored in the memory cell array 300 maybe data of at least one page or at least one block of the memory cellarray 300. The second error correction circuit 400 performs an ECCencoding on the processing result data to generate a second parity dataand stores the processing result data and the second parity data in atarget page of the memory cell array 300.

The second error correction circuit 400 may generate the second paritydata by selecting the same ECC of a plurality of ECCs stored therein asthe ECC which the first error correction circuit 110 uses whengenerating the parity data PRT.

FIG. 3 is a block diagram illustrating the semiconductor memory devicein FIG. 2 according to exemplary embodiments.

Referring to FIG. 3, the semiconductor memory device 200 a may include acontrol logic circuit 210, an address register 220, a bank control logic230, a refresh counter 297, a row address multiplexer 240, a columnaddress latch 250, a row decoder 260, a column decoder 270, a memorycell array 300, a sense amplifier unit 285, an input/output (I/O) gatingcircuit 290, the internal processing circuit 390, the second errorcorrection circuit 400, a path selection circuit 280, and a datainput/output (I/O) buffer 299.

The semiconductor memory device 200 a includes the internal processingcircuit 390 and supports a processing in-memory (PIM) of pop-count (orpop-counting) operation and a logical bitwise operation on at least onebit-vector. When the semiconductor memory device 200 a executes theprocessing in-memory, the second error correction circuit 400 employinga plurality of ECCs in the semiconductor memory device 200 a may performan ECC encoding using the same ECC as the first ECC 120 of the memorycontroller 100 although a manufacture of the memory controller 100varies. The second error correction circuit 400 may be configurable.

In some embodiments, the refresh counter 297 may not be included in thesemiconductor memory device 200 a.

The memory cell array 300 may include first through eighth bank memoryarrays 310˜380. The row decoder 260 may include first through eighthbank row decoders 260 a˜260 h respectively coupled to the first througheighth bank memory arrays 310˜380, the column decoder 270 may includefirst through eighth bank column decoders 270 a˜270 h respectivelycoupled to the first through eighth bank memory arrays 310˜380, and thesense amplifier unit 285 may include first through eighth bank senseamplifiers 285 a˜285 h respectively coupled to the first through eighthbank memory arrays 310˜380. Each of the first through eighth bank memoryarrays 310˜380 may include a plurality of memory cells MC, and each ofthe memory cells MC is coupled to a corresponding word-line WL and acorresponding bit-line BTL. The first through eighth bank memory arrays310˜380, the first through eighth bank row decoders 260 a˜260 h, thefirst through eighth bank column decoders 270 a˜270 h and first througheighth bank sense amplifiers 285 a˜285 h may form first through eighthbanks. Although the semiconductor memory device 200 a shown in FIG. 3illustrates eighth banks, the semiconductor memory device 200 a mayinclude other number of banks.

The address register 220 may receive an address ADDR including a bankaddress BANK_ADDR, a row address ROW_ADDR and a column address COL_ADDRfrom the memory controller 100. The address register 220 may provide thereceived bank address BANK_ADDR to the bank control logic 230, mayprovide the received row address ROW_ADDR to the row address multiplexer240, and may provide the received column address COL_ADDR to the columnaddress latch 250.

The bank control logic 230 may generate bank control signals in responseto the bank address BANK_ADDR. One of the first through eighth bank rowdecoders 260 a˜260 h corresponding to the bank address BANK_ADDR may beactivated in response to the bank control signals, and one of the firstthrough eighth bank column decoders 270 a˜270 h corresponding to thebank address BANK_ADDR may be activated in response to the bank controlsignals.

The refresh counter 297 may generate a refresh row address REF_ADDR forrefreshing memory cell rows in the memory cell array 300 under controlof the control logic circuit 210. The refresh counter 297 may beincluded when the memory cells MC are implemented with dynamic memorycells.

The row address multiplexer 240 may receive the row address ROW_ADDRfrom the address register 220, and may receive the refresh row addressREF_ADDR from the refresh counter 297. The row address multiplexer 240may selectively output the row address ROW_ADDR or the refresh rowaddress REF_ADDR as a row address RA. The row address RA that is outputfrom the row address multiplexer 240 may be applied to the first througheighth bank row decoders 260 a˜260 h.

The activated one of the first through eighth bank row decoders 260a˜260 h may decode the row address RA that is output from the rowaddress multiplexer 240, and may activate a word-line corresponding tothe row address RA. For example, the activated bank row decoder mayapply a word-line driving voltage to the word-line corresponding to therow address RA.

The column address latch 250 may receive the column address COL_ADDRfrom the address register 220, and may temporarily store the receivedcolumn address COL_ADDR. In some embodiments, in a burst mode, thecolumn address latch 250 may generate column addresses that incrementfrom the received column address COL_ADDR. The column address latch 250may apply the temporarily stored or generated column address COL_ADDR tothe first through eighth bank column decoders 270 a˜270 h.

The activated one of the first through eighth bank column decoders 270a˜270 h may decode the column address COL_ADDR that is output from thecolumn address latch 250, and may control the I/O gating circuit 290 inorder to output data corresponding to the column address COL_ADDR.

The I/O gating circuit 290 may include a circuitry for gatinginput/output data. The I/O gating circuit 290 may further include readdata latches for storing data that is output from the first througheighth bank memory arrays 310˜380, and write drivers for writing data tothe first through eighth bank memory arrays 310˜380. The I/O gatingcircuit 290 may include a cross-bar switch to change a memory locationin which the main data MD and the parity data are stored in the memorycell array 300.

Data read from one bank memory array of the first through eighth bankmemory arrays 310˜380 may be sensed by sense amplifiers coupled to theone bank memory array from which the data is to be read, and may bestored in the read data latches. The data stored in the read datalatches may be provided to the memory controller 100 selectively via theinternal processing circuit 390 and the error correction circuit 400 andthrough the data I/O buffer 299 according to an internal processingmode. Codeword CW to be written in one bank memory array of the firstthrough eighth bank memory arrays 310˜380 may be provided to the dataI/O buffer 299 from the memory controller 100.

The data I/O buffer 299 provides a first codeword CW1 to the I/O gatingcircuit 290 in a write operation and provides a second codeword CW2 fromthe error correction circuit 400 or the first codeword CW1 from the pathselection circuit 280 to the memory controller 100 in a read operation.

The path selection circuit 280 provides the first codeword CW1 to thedata I/O buffer 299 in a normal mode and provides the first codeword CW1to the internal processing circuit 390 in an internal processing mode inresponse to an internal processing mode signal IPS.

The internal processing circuit 390 is selectively enabled in responseto the internal processing mode signal IPS, performs the internalprocessing on a main data of the first codeword CW1 from the pathselection circuit 280 and provides the second error correction circuit400 with a processing result data indicating a result of the internalprocessing.

The second error correction circuit 400 performs an ECC encoding on theprocessing result data to generate a second parity data and stores thesecond codeword CW2 including the processing result data and the secondparity data in a target page through the I/O gating circuit 290 in theinternal processing mode, in response to the internal processing modesignal IPS. The second error correction circuit 400 may transmit thesecond codeword CW2 to the memory controller 100 through the data I/Obuffer 299.

The error correction circuit 400, in a write operation of thesemiconductor memory device 200 a, may generate a parity data based onthe main data MD received from the data I/O buffer 299, and may providethe I/O gating circuit 290 with the codeword CW including the main dataMD and the parity data. The I/O gating circuit 290 may write the maindata MD of the codeword CW in a first sub array and write the paritydata of the codeword CW in a second sub array. The first sub array andthe second sub array may be belonged to different bank memory arrays.

The control logic circuit 210 may control operations of thesemiconductor memory device 200 a. For example, the control logiccircuit 210 may generate control signals for the semiconductor memorydevice 200 a in order to perform a write operation or a read operation.The control logic circuit 210 may include a command decoder 211 thatdecodes a command CMD received from the memory controller 100 and a moderegister 212 that sets an operation mode of the semiconductor memorydevice 200 a.

For example, the command decoder 211 may generate the control signalscorresponding to the command CMD by decoding a write enable signal(/WE), a row address strobe signal (/RAS), a column address strobesignal (/CAS), a chip select signal (/CS), etc. The control logiccircuit 210 may generate a first control signal CTL1 to control the I/Ogating circuit 290 and a second control signal CTL2 to control thesecond error correction circuit 400. When the mode register 212 is setto the internal operation mode in response to the command CMD, the moderegister 212 outputs the internal processing mode signal IPS with afirst logic level. The control logic circuit 210 may provide theinternal processing mode signal IPS to the path selection circuit 280and the internal processing circuit 390.

FIGS. 4A to 4E are circuit diagrams of examples of a memory cell shownin FIG. 3, according to exemplary embodiments.

FIGS. 4A to 4D illustrate memory cells MC which are implemented withresistive type memory cells and FIG. 4E illustrates a memory cell MCwhich is implemented with a dynamic memory cell.

FIG. 4A illustrates a resistive type memory cell without a selectionelement, while FIGS. 4B to 4D show resistive type memory cells eachcomprising a selection element.

Referring to FIG. 4A, a memory cell MC may include a resistive elementRE connected to a bit-line BTL and a word-line WL. Such a resistivememory cell having a structure without a selection element may storedata by a voltage applied between bit-line BL and word-line WL.

Referring to FIG. 4B, a memory cell MC may include a resistive elementRE and a diode D. The resistive element RE may include a resistivematerial for data storage. The diode D may be a selection element (orswitching element) that supplies current to resistive element RE or cutsoff the current supply to resistive element RE according to a bias ofword-line WL and bit-line BTL. The diode D may be coupled between theresistive element RE and word-line WL, and the resistive element RE maybe coupled between the bit-line BTL and the diode D. Positions of thediode D and the resistive element RE may be interchangeable. The diode Dmay be turned on or turned off by a word-line voltage. Thus, a resistivememory cell may be not driven where a voltage of a constant level orhigher is supplied to an unselected word-line WL.

Referring to FIG. 4C, a memory cell MC may include a resistive elementRE and a bidirectional diode BD. The resistive element R may include aresistive material for data storage. The bidirectional diode BD may becoupled between the resistive element RE and a word-line WL, and theresistive element RE may be coupled between a bit-line BTL andbidirectional diode BD. Positions of the bidirectional diode BD and theresistive element RE may be interchangeable. The bidirectional diode BDmay block leakage current flowing to an unselected semiconductor memorycell.

Referring to FIG. 4D, a memory cell MC may include a resistive elementRE and a transistor CT. The transistor CT may be a selection element (orswitching element) that supplies current to the resistive element RE orcuts off the current supply to the resistive element RE according to avoltage of a word-line WL. The transistor CT may be coupled between theresistive element RE and a word-line WL, and the resistive element REmay be coupled between a bit-line BTL and the transistor CT. Positionsof the transistor CT and the resistive element RE may beinterchangeable. The semiconductor memory cell may be selected orunselected depending on whether the transistor CT drive by word-line WLis turned on or turned off.

Referring to FIG. 4E, a memory cell MC may include a cell capacitor CCand a transistor CT. The transistor CT may be a selection element (orswitching element) that connects/disconnects the cell capacitor CCto/from bit-line BTL according to a voltage of a word-line WL. Thetransistor CT may be coupled between the cell capacitor CC, a word-lineWL and a bit-line BTL, and the cell capacitor CC may be coupled betweenthe transistor CT and a plate voltage (not illustrated).

FIG. 5 illustrates an example of a memory cell (referred to as STT-MRAMcell) shown in FIG. 3, according to exemplary embodiments.

Referring to FIG. 5, an STT-MRAM cell 30 may include a MTJ element 40and a cell transistor CT. A gate of the cell transistor CT is connectedto a word-line WL and one electrode of the cell transistor CT isconnected through the MTJ 40 to a bit-line BTL. Also, the otherelectrode of the cell transistor CT is connected to a source line SL.

The MTJ element 40 may include the free layer 41, the pinned layer 43,and a tunnel layer 42 disposed between the free layer 41 and the pinnedlayer 43. A magnetization direction of the pinned layer 43 may be fixed,and a magnetization direction of the free layer 41 may be parallel to oranti-parallel to the magnetization direction of the pinned layer 43according to written data. In order to fix the magnetization directionof the pinned layer 43, for example, an anti-ferromagnetic layer (notshown) may be further provided.

In order to perform a write operation of the STT-MRAM cell 30, a logichigh voltage is applied to the word-line WL to turn on the celltransistor CT. A program current, for example, a write current isapplied to the bit-line BL and the source line SL. A direction of thewrite current is determined by a logic state of the MTJ element 40.

In order to perform a read operation of the STT-MRAM cell 30, a logichigh voltage is applied to the word-line WL to turn on the celltransistor CT, and a read current is supplied to the bit-line BL and thesource line SL. Accordingly, a voltage is developed at both ends of theMTJ element 40, is detected by the sense amplifier 285 a, and iscompared with a reference voltage from a reference voltage to determinea logic state of the MTJ element 40. Accordingly, data stored in the MTJelement 40 may be detected.

FIG. 6A illustrates a portion of the semiconductor memory device of FIG.3 in a non-internal processing mode (a normal mode) according toexemplary embodiments.

In FIG. 6A, the control logic circuit 210, the first bank memory array310, the I/O gating circuit 290, the path selection circuit 280, theinternal processing circuit 390, and the error correction circuit 400are illustrated.

Referring to FIG. 6A, the internal processing mode signal IPS may have asecond logic level (low level) in the normal mode and the internalprocessing circuit 390 is disabled. The first bank memory array 310includes a plurality of memory cells coupled to a plurality ofword-lines and a plurality of bit-lines, and each of the memory cellsinclude a dynamic memory cell or a resistive type memory cell.

The I/O gating circuit 290 includes a cross-bar switch 293 coupledbetween the first bank memory array 310 and a plurality of switchingcircuits 291 a˜291 d. The plurality of switching circuits 291 a˜291 dmay be coupled to the path selection circuit 280 and the data I/O buffer299. In the semiconductor memory device 200 a, bit lines correspondingto data of a burst length (BL) may be simultaneously accessed to supportthe BL indicating the maximum number of column positions that isaccessible. For example, if the BL is set to 8, data bits may be set to128 bits.

In a write operation of the normal mode, the data I/O buffer 299provides the first codeword CW1 to the switching circuits 291 a˜291 d.The switching circuits 291 a˜291 d may provide the first codeword CW1 tothe cross-bar switch 293 in response to a first control signal CTL1 fromthe control logic circuit 210. The cross-bar switch 293 may transfer afirst codeword CW1 to a target page TPG in the first bank memory array310 in response to the first control signal CTL1. When the cross-barswitch 293 transfers the first codeword CW1 to the target page TPG inthe first bank memory array 310, the cross-bar switch 293 may transfer afirst parity data in the first codeword CW1 to an upper address region(i.e., a location corresponding to an upper address) UAR or to a loweraddress region (i.e., a location corresponding to a lower address) LARof the target page TPG. The first parity data of the first codeword CW1may transfer to the upper address region UAR or to the lower addressregion LAR of the target page TPG in response to the first controlsignal CTL1.

When the cross-bar switch 293 transfers the first parity data of thefirst codeword CW1 to the upper address region UAR of the target pageTPG, a first main data of the first codeword CW1 may be stored in aremaining region (or memory location) of the target page TPG except theupper address region UAR. When the cross-bar switch 293 transfers thefirst parity data of the first codeword CW1 to the lower address regionLAR of the target page TPG, the first main data of the first codewordCW1 may be stored in a remaining region of the target page TPG exceptthe lower address region LAR.

In a read operation of the normal mode, the first codeword CW1 from thetarget page TPG of the first bank memory array 310 is provided to thepath selection circuit 280 through the I/O gating circuit 290. The pathselection circuit 280 provides the first codeword CW1 to the data I/Obuffer 299 in response to the internal processing mode signal IPS.

FIG. 6B illustrates a portion of the semiconductor memory device of FIG.3 in a non-internal processing mode (e.g., a normal mode) according toother exemplary embodiments.

In the present embodiment, the same descriptions as described in theaforementioned embodiments will be omitted or mentioned briefly for thepurpose of ease and convenience in explanation. Hereinafter, thecomponents described with reference to FIG. 6A will be not describedagain.

Referring to FIG. 6B, in a write operation of the normal mode, the dataI/O buffer 299 provides a first codeword CW1 to the second errorcorrection circuit 400. The first codeword CW1 may include a first maindata and a first parity data. The second error correction circuit 400may perform an error correction on the first codeword CW1 and generate acorrected codeword C_CW1 including a second main data and a secondparity data, and provide corrected codeword C_CW1 to the I/O gatingcircuit 290. The switching circuits 291 a˜291 d may provide thecorrected codeword C_CW1 to the cross-bar switch 293 in response to thefirst control signal CTL1. When an error has not occurred after thesecond error correction circuit 400 performed the error correction, dataof the first codeword CW1 and the corrected codeword C_CW1 may be thesame as each other.

When the cross-bar switch 293 transfers the second parity data of thecorrected codeword C_CW1 to the upper address region UAR of a targetpage TPG, the second main data of the corrected codeword C_CW1 may bestored in a remaining region of the target page TPG (e.g., the targetpage portion not including the upper address region UAR). When thecross-bar switch 293 transfers the second parity data of the correctedcodeword C_CW1 to the lower address region LAR of the target page TPG,the second main data of the corrected codeword C_CW1 may be stored in aremaining region of the target page TPG (e.g., the target page portionnot including the lower address region LAR).

In a read operation of the internal processing mode in FIG. 6B, the I/Ogating circuit 290 provides a first codeword CW1 including a first maindata and a first parity data stored in the target page TPG to the seconderror correction circuit 400. The second error correction circuit 400may perform an error correction on the first codeword CW1 to generate acorrected codeword C_CW1 including a second main data and a secondparity data, and provide to the data I/O buffer 299. The correctedcodeword C_CW1 may be stored in the target page TPG through the I/Ogating circuit 290.

FIG. 7A illustrates a portion of the semiconductor memory device of FIG.3 in an internal processing mode according to exemplary embodiments.

In the present embodiment, the same descriptions as described in theaforementioned embodiments will be omitted or mentioned briefly for thepurpose of ease and convenience in explanation. Hereinafter, thecomponents described with reference to FIG. 6A will be not describedagain.

Referring to FIG. 7A, the internal processing mode signal IPS may have afirst logic level (high level) in the internal processing mode and theinternal processing circuit 390 is enabled.

In a write operation of the internal processing mode in FIG. 7A, thedata I/O buffer 299 provides a first codeword CW1 to the internalprocessing circuit 390. The internal processing circuit 390 may performan internal processing on a first main data of the first codeword CW1and output a processing result data MD2 to the second error correctioncircuit 400. The internal processing circuit 390 may perform anincrement operation that changes the first main data of the firstcodeword CW1 in increments of 1 and generates a processing result dataMD2. The second error correction circuit 400 may perform an ECC encodingon the processing result data MD2 to generate a second parity data andprovides the second codeword CW2 including the processing result dataMD2 and the second parity data to the I/O gating circuit 290. Theswitching circuits 291 a˜291 d may provide the second codeword CW2 tothe cross-bar switch 293 in response to a first control signal CTL1 fromthe control logic circuit 210. The cross-bar switch 293 may transfer thesecond codeword CW2 to a target page TPG in the first bank memory array310, in response to the first control signal CTL1. When the cross-barswitch 293 transfers the second codeword CW2 to the target page TPG inthe first bank memory array 310, the cross-bar switch 293 may transferthe second parity data in the second codeword CW2 to an upper addressregion (i.e., a location corresponding to an upper address) UAR or to alower address region (i.e., a location corresponding to a lower address)LAR of the target page TPG. The second parity data of the secondcodeword CW2 may be transferred to the upper address region UAR or tothe lower address region LAR of the target page TPG in response to thefirst control signal CTL1.

In a read operation in the internal processing mode, the I/O gatingcircuit 290 provides a first codeword CW1 stored in the target page TPGto the path selection circuit 280, and the path selection circuit 280provides the first codeword CW1 to the internal processing circuit 390in response to the internal processing mode signal IPS. The internalprocessing circuit 390 is enabled in response to the internal processingmode signal IPS, performs an internal processing on a first main data ofthe first codeword CW1 and outputs a processing result data MD2 to thesecond error correction circuit 400. The internal processing circuit 390may include at least one buffer 391 and at least one processing block393 as illustrated in FIG. 16.

The second error correction circuit 400 performs an ECC encoding on theprocessing result data MD2 to generate a second parity data and providesthe second codeword CW2 including the processing result data MD2 and thesecond parity data to the I/O gating circuit 290 and the data I/O buffer299.

FIG. 7B illustrates a portion of the semiconductor memory device of FIG.3 in an internal processing mode according to other exemplaryembodiments.

In the present embodiment, the same descriptions as described in theaforementioned embodiments will be omitted or mentioned briefly for thepurpose of ease and convenience in explanation. Hereinafter, thecomponents described with reference to FIG. 7A will be not describedagain.

Referring to FIG. 7B, in a write operation of the internal processingmode, the data I/O buffer 299 provides a first codeword CW1 to thesecond error correction circuit 400. The second error correction circuit400 may perform an ECC decoding on the first codeword CW1 and provide acorrected codeword C_CW1 to the internal processing circuit 390. Theinternal processing circuit 390 may perform an internal processing on afirst main data of the corrected codeword C_CW1 and output a processingresult data MD2 to the second error correction circuit 400. The internalprocessing circuit 390 may perform an increment operation that changesthe first main data of the corrected codeword C_CW1 in increments of 1.The second error correction circuit 400 may perform an ECC encoding onthe processing result data MD2 to generate a second parity data andprovide a second codeword CW2 including the processing result data MD2and the second parity data to the I/O gating circuit 290. The switchingcircuits 291 a˜291 d may provide the second codeword CW2 to thecross-bar switch 293. The cross-bar switch 293 may transfer the secondcodeword CW2 to a target page TPG in the first bank memory array 310.When the cross-bar switch 293 transfers the second codeword CW2 to thetarget page TPG in the first bank memory array 310, the cross-bar switch293 may transfer the second parity data in the second codeword CW2 to anupper address region (i.e., a location corresponding to an upperaddress) UAR or to a lower address region (i.e., a locationcorresponding to a lower address) LAR of the target page TPG. The secondparity data of the second codeword CW2 may be transferred to the upperaddress region UAR or to the lower address region LAR of the target pageTPG in response to the first control signal CTL1.

In a read operation of the internal processing mode in FIG. 7B, the I/Ogating circuit 290 provides a first codeword CW1 stored in the targetpage TPG to the second error correction circuit 400. The second errorcorrection circuit 400 may perform an ECC decoding on the first codewordCW1 and provide a corrected codeword C_CW1 to the internal processingcircuit 390. The internal processing circuit 390 may perform an internalprocessing on a first main data of the corrected codeword C_CW1 andoutput a processing result data MD2 to the second error correctioncircuit 400. The second error correction circuit 400 may perform an ECCencoding on the processing result data MD2 to generate a second paritydata and provides the second codeword CW2 including the processingresult data MD2 and the second parity data to the data I/O buffer 299.The second codeword CW2 may be stored in the target page TPG through theI/O gating circuit 290.

FIG. 8 illustrates the second error correction circuit shown in FIG. 3according to exemplary embodiments.

Referring to FIG. 8, the second error correction circuit 400 may includean ECC engine 420, a buffer unit 440 and a plurality of storage device471˜47 k. The buffer unit 440 may include first and second buffers 441and 443.

The first buffer 441 may be enabled in a read operation of the internalprocessing mode in response to a mode signal MS and provide processingresult data MD2 to the ECC engine 420. The second buffer 443 may beenabled in a read operation of the normal mode in response to the modesignal MS, and the second buffer 443 may provide the first codeword CW1to the ECC engine 420.

The ECC engine 420 may perform an ECC encoding and an ECC decoding byselection the same ECC of a plurality of ECCs stored in the storagedevices 471˜47 k as the first ECC 120 in the memory controller 100, inresponse to a control signal CTL2 from the control logic circuit 210(e.g., a selection signal SS). The plurality of ECCs stored in thestorage devices 471˜47 k may include at least one of a single errorcorrection (SEC) code, a single error correction and double errordetection (SECDED) code, and double error correction (DEC) code. The ECCengine 420 performs the ECC encoding on the processing result data MD2using the same ECC to generate the second parity data and provides thesecond codeword CW2 including the processing result data MD2 and thesecond parity data to the data I/O buffer 299 in the read operation ofthe internal processing mode. The second codeword CW2 may be stored in atarget page TPG of the first bank memory array 310 through the I/Ogating circuit 290.

In one embodiment, when the first ECC 120 in the memory controller 100is a single error correction (SEC) code, the memory controller 100transmits to the control logic circuit 210 an internal processingcommand including information of the first ECC 120, and the commanddecoder 211 in the control logic circuit 210 provides the second errorcorrection circuit 400 with the second control signal CTL2 including theselection signal SS that includes the information of the first ECC 120.For example, the ECC engine 420 selects the same ECC ECCa in response tothe selection signal SS and performs the ECC encoding.

In one embodiment, when the first ECC 120 in the memory controller 100is double error correction (DEC) code, the memory controller 100transmits to the control logic circuit 210 an internal processingcommand including information of the first ECC 120, and the commanddecoder 211 in the control logic circuit 210 provides the second errorcorrection circuit 400 with the second control signal CTL2 including theselection signal SS that includes the information of the first ECC 120.For example, ECC engine 420 selects the same ECC ECCb in response to theselection signal SS and performs the ECC encoding.

In one embodiment, when the first ECC 120 in the memory controller 100is a single error correction and double error detection (SECDED) code,the memory controller 100 transmits to the control logic circuit 210 aninternal processing command including information of the first ECC 120,and the command decoder 211 in the control logic circuit 210 providesthe second error correction circuit 400 with the second control signalCTL2 including the selection signal SS that includes the information ofthe first ECC 120. For example, the ECC engine 420 selects the same ECCECCk in response to the selection signal SS and performs the ECCencoding.

FIG. 9 illustrates an ECC engine in the second error correction circuitof FIG. 8 according to exemplary embodiments.

Referring to FIG. 9, the ECC engine 420 may include an ECC decoder 425and an ECC encoder 430.

The ECC decoder 425 performs an ECC decoding on the first codeword CW1and provides the corrected first codeword C_CW1 to the data I/O buffer299 in the read operation of the normal mode. The ECC encoder 430selects the same ECC of the ECCs stored in the storage device 471˜47 kas the first ECC 120 in response to the selection signal SS, performs anECC encoding on the processing result data MD2 using the same ECC togenerate the second parity data PRT2 and the second codeword CW2including the processing result data MD2 and the second parity data PRT2to the I/O gating circuit 290 and the data I/O buffer 299 in the readoperation of the internal processing mode.

As mentioned above, the semiconductor memory device 200 a supportsin-memory processing and may greatly reduce transmission throughmemory-controller interface. Therefore, the semiconductor memory device200 a may save memory bandwidth and increase usability by generating thesecond parity data using the same ECC of the ECCs as the first ECC 120in the memory controller 100.

FIG. 10 is a diagram illustrating a memory system according to exemplaryembodiments.

Referring to FIG. 10, a memory system 500 may include a memorycontroller 30 and a semiconductor memory device 40. The semiconductormemory device 40 may include a command-address input-output block AWORD41, data input-output blocks DWORD0˜DWORD3 42˜45 and an internal circuit50. The memory controller 30 may include a command-address input-outputblock 31, data input-output blocks 32 and an internal circuit 35. Forexample, the semiconductor memory device 40 may be compatible with highbandwidth memory (HBM) standards.

The command CMD, an address ADDR, a system clock signal CLK, a clockenable signal CKE, etc. may be transferred from the command-addressinput-output block 31 of the memory controller 30 to the command-addressinput-output block 41 of the semiconductor memory device 40. Data DQ, adata bus inversion signal DBI, a data mask signal DM, a write datastrobe signal WDQS, a read data strobe signal RDQS, etc. may betransferred between the data input-output blocks 32 of the memorycontroller 30 and the data input-output blocks 42˜45 of thesemiconductor memory device 40.

The multiple-input shift register (MISR) and/or the linear feedbackshift register (LFSR) may be implemented in the input-output blocks41˜45 of the semiconductor memory device 40. Using the MISR/LFSRcircuits, the links between the memory controller 30 and thesemiconductor memory device 40 may be tested and trained.

For example, as illustrated in FIG. 10, the MISR/LFSR circuitcorresponding to one byte included in the data input-output blocks 42˜45may have a size of 20 bits. The 20 bits may include rising bits R andfalling bits F of the byte data signal, the data bus inversion signalDBI and the data mask signal DM. The MISR/LFSR circuit of the commandaddress input-output block 41 may have a size of 30 bits. The 30 bitsmay include rising bits R and falling bits F of the row command bitsR0˜R5, the column command bits C0˜C7 and the clock enable signal CKE.

For example, one channel includes four data input-output blocks 42˜45corresponding to four words, and each of the four data input-outputblocks 42˜45 may include four MISR/LFSR circuits corresponding to fourbytes BYTE0˜BYTE3.

The semiconductor memory device 40 may be the semiconductor memorydevice 200 a of FIG. 3 and the internal circuit 50 may include theinternal processing circuit 390 and the second error correction circuit400. The internal circuit 35 may include the first error correctioncircuit 120 as in FIG. 2. Therefore, in the memory system 500, thesemiconductor memory device 40 may support in-memory processing and maygreatly reduce transmission through memory-controller interface.Therefore, the memory system 500 may save memory bandwidth and increaseusability by generating the second parity data using the same ECC of theECCs as the first ECC 120 in the memory controller 100.

FIG. 11 is a diagram illustrating an example of a high bandwidth memory(HBM) organization.

Referring to FIG. 11, an HBM 600 may be configured to have a stack ofmultiple DRAM semiconductor dies 620, 630, 640 and 650. The HBM of thestack structure may be optimized by a plurality of independentinterfaces called channels. Each DRAM stack may support up to 8 channelsin accordance with the HBM standards. FIG. 11 shows an example stackcontaining 4 DRAM semiconductor dies 620, 630, 640 and 650, and eachDRAM semiconductor die supports two channels CHANNEL0 and CHANNEL1.

Each channel provides access to an independent set of DRAM banks.Requests from one channel may not access data attached to a differentchannel. Channels are independently clocked, and need not besynchronous.

The HBM 600 may further include an interface die 610 or a logic diedisposed at bottom of the stack structure to provide signal routing andother functions. Some function for the DRAM semiconductor dies 620, 630,640 and 650 may be implemented in the interface die 610. An internalprocessing circuit and a second error correction circuit described withreference to FIG. 3 may be implemented in the interface die 610, and theprocessing circuit and the second error correction circuit may performthe internal processing operation and may generate the second paritydata.

FIG. 12 is a structural diagram illustrating a semiconductor memorydevice according to exemplary embodiments.

Referring to FIG. 12, a semiconductor memory device 700 may includefirst through s-th semiconductor integrated circuit layers LA1 throughLas (s is an integer equal to or greater than three), in which thelowest first semiconductor integrated circuit layer LA1 is assumed to bean interface or control chip and the other semiconductor integratedcircuit layers LA2 through LAs are assumed to be slave chips includingcore memory chips. The first through s-th semiconductor integratedcircuit layers LA1 through LAs may transmit and receive signalstherebetween through through-substrate vias (e.g., through-silicon vias)TSVs. The lowest first semiconductor integrated circuit layer LA1 as theinterface or control chip may communicate with an external memorycontroller through a conductive structure formed on an external surface.A description will be made regarding structure and an operation of thesemiconductor memory device 700 by mainly using the first semiconductorintegrated circuit layer LA1 or 710 as the interface or control chip andthe s-th semiconductor integrated circuit layer LAs or 720 as the slavechip.

The first semiconductor integrated circuit layer 710 may include variousperipheral circuits for driving memory regions 721 provided in the kthsemiconductor integrated circuit layer 720. For example, the firstsemiconductor integrated circuit layer 710 may include a row (X)-driver7101 for driving word-lines of a memory, a column (Y)-driver 7102 fordriving bit-lines of the memory, a data input/output unit (Din/Dout)7103 for controlling input/output of data, a command (CMD) buffer 7104for receiving a command CMD from outside and buffering the command CMD,and an address (ADDR) buffer (or, address register) 7105 for receivingan address from outside and buffering the address. The memory region 721may include a plurality of bank memory arrays in which a plurality ofmemory cells are arranged, and each of the plurality of bank memoryarrays may include a plurality of bank memory arrays as described withreference to FIG. 3.

The first semiconductor integrated circuit layer 710 may further includea control logic circuit 7107. The control logic circuit 7107 may accessthe memory region 721 and may generate control signals for accessing thememory region 721 based on the command from the memory controller.

The s-th semiconductor integrated circuit layer 720 may include aninternal processing circuit 723 and an error correction circuit 722. Theinternal processing circuit 723 performs an internal processing on afirst codeword stored in the memory region 721 to generate a processingresult data when a command designate an internal processing mode. Theerror correction circuit 722 performs an ECC encoding on the processingresult data to generate a second parity data. The error correctioncircuit 722 may be the same as the error correction circuit 400disclosed above. The error correction circuit 722 selects the same ECCof a plurality of ECC as an ECC used for generating the first paritydata and performs the ECC encoding using the same ECC. Therefore,although when an ECC is changed due to change of a memory controller,the error correction circuit 722 may selects the same ECC an ECC usedfor generating the first parity data and usability of the semiconductormemory device 700 may be increased.

In addition, a three dimensional (3D) memory array is provided insemiconductor memory device 700. The 3D memory array is monolithicallyformed in one or more physical levels of arrays of memory cells havingan active area disposed above a silicon substrate and circuitryassociated with the operation of those memory cells, whether suchassociated circuitry is above or within such substrate. The term“monolithic” means that layers of each level of the array are directlydeposited on the layers of each underlying level of the array. Thefollowing patent documents, which are hereby incorporated by reference,describe suitable configurations for the 3D memory arrays, in which thethree-dimensional memory array is configured as a plurality of levels,with word-lines and/or bit-lines shared between levels: U.S. Pat. Nos.7,679,133; 8,553,466; 8,654,587; 8,559,235; and US Pat. Pub. No.2011/0233648.

FIG. 13 is a flow chart illustrating a method of operating asemiconductor memory device according to exemplary embodiments.

Referring to FIGS. 2 through 13, in a method of operating asemiconductor memory device 200 a including a memory cell array 300having a plurality of memory cells coupled to a plurality of word-linesand a plurality of bit-lines and a control logic circuit 210 to controlaccess to the memory cell array 300, the control logic circuit 210receives a command from a memory controller 100, an internal processingcommand CMD to perform a pop-count operation on bit vectors (e.g., oneor more sets of data) stored in the memory cell array (S110). Thesemiconductor memory device 200 a also receives an address ADDRdesignating a target page of the memory cell array 300 along with theinternal processing command CMD from the memory controller 100.

A row decoder 260 and an I/O gating circuit 290 of the semiconductormemory device 200 a provides the internal processing circuit 390 with abit vector including a main data and a first parity data stored in thetarget page. The internal processing circuit 390 performs an internalprocessing corresponding to the command CMD on the main data andprovides an error correction circuit 400 with a processing result datacorresponding to a result of the internal processing (S120).

The error correction circuit 400 generates a second parity data based onthe processing result data (S130). The error correction circuit 400selects the same ECC of a plurality of ECCs as a first ECC used forgenerating the first parity data and performs an ECC encoding using thesame ECC to generate the second parity data.

The error correction circuit 400 provides the I/O gating circuit 290with a second codeword including the processing result data and thesecond parity data to store the processing result data and the secondparity in the target page of the memory cell array 300 (S140).

The error correction circuit 400 may transmit the processing result dataand the second parity data to the memory controller 100 through the dataI/O buffer 299 (S150).

FIG. 14 is a flow chart illustrating in-memory processing of a pop-countoperation in a method of FIG. 13 according to exemplary embodiments.

Referring to FIG. 14, for performing the pop-count operation (S120), theinternal processing circuit 390 initiates the pop-count operation(S121). Initiating the pop-count operation is performed by resettingregisters in the internal processing circuit 390. A pop-count (orpopulation count) operation counts the number of ones (1s) in a bitsequence (or a bit vector).

The internal processing circuit 390 performs pop-counting (on aspecified bit vector) over a predefined, small data type such as, forexample, on each 8-bit portion of data bits of the main data from thetarget page (S123). The internal processing circuit 390 may use areduction tree to accumulate intermediate results and generates thefinal pop-count (S125).

When executing pop-counts over large vectors that span multiple DRAMpages, the semiconductor memory device 200 a may need to know all thepage addresses that the vector is stored at. Hence, after the first DRAMpage of the vector is processed, the semiconductor memory device 200 amay need to figure out the subsequent pages where the vector resides. Inone embodiment, a direct memory access (DMA)-like mechanism may beimplemented when multiple pages need to be traversed. In such animplementation, the physical addresses of the DRAM pages in which thevector is occupied may be sent to the semiconductor memory device 200 a,for example, by the memory controller 100. These pages may be thentraversed by an internal controller within the semiconductor memorydevice 200 a such as the control logic circuit 210.

FIG. 15 is a flow chart illustrating a method of operating asemiconductor memory device according to exemplary embodiments.

Referring to FIGS. 2 through 12 and 15, in a method of operating asemiconductor memory device 200 a including a memory cell array 300having a plurality of memory cells coupled to a plurality of word-linesand a plurality of bit-lines and a control logic circuit 210 to controlaccess to the memory cell array 300, the control logic circuit 210receives a command from a memory controller 100, an internal processingcommand CMD to perform a logical bitwise operation on two or more bitvectors stored in the memory cell array (S210). The semiconductor memorydevice 200 a also receives an address ADDR designating two or moretarget pages of the memory cell array 300 along with the internalprocessing command CMD from the memory controller 100.

A row decoder 260 and an I/O gating circuit 290 of the semiconductormemory device 200 a provides an internal processing circuit 390 with twoor more bit vectors, each including a main data and a first parity datastored in two or more target pages. The internal processing circuit 390performs an internal processing corresponding to the command CMD on themain data and provides an error correction circuit 400 with a processingresult data corresponding to a result of the internal processing (S220).

A row decoder 260 and an I/O gating circuit 290 of the semiconductormemory device 200 a provides the internal processing circuit 390 withtwo or more bit vectors, each including a main data and a first paritydata stored in the target pages. The internal processing circuit 390performs an internal processing corresponding to the command CMD on themain data and provides an error correction circuit 400 with a processingresult data corresponding to a result of the internal processing (S220).The logical bitwise operation may be one of an OR operation, an ANDoperation, a NOT operation, a NAND operation, a NOR operation and an XORoperation.

The error correction circuit 400 generates a second parity data based onthe processing result data (S230). The error correction circuit 400selects the same ECC of a plurality of ECCs as a first ECC used forgenerating the first parity data and performs an ECC encoding using thesame ECC to generate the second parity data.

The error correction circuit 400 provides the I/O gating circuit 290with a second codeword including the processing result data and thesecond parity data to store the processing result data and the secondparity in the target page of the memory cell array 300 (S240).

The error correction circuit 400 may transmit the processing result dataand the second parity data to the memory controller 100 through the dataI/O buffer 299 (S250). In an embodiment, the second parity data may betransmitted to the memory controller 100 simultaneously with theprocessing result data. In an embodiment, the second parity data may betransmitted to the memory controller 100 after the processing resultdata is transmitted to the memory controller 100.

FIG. 16 illustrates that a logical bitwise operation is performed in thesemiconductor memory device of FIG. 3 according to exemplaryembodiments.

Referring to FIGS. 3, 7 and 16, for a logical bitwise operation betweentwo 8-bit operands stored in the first bank memory array 310, the 8 bitsof one of the two operands may be transferred or read from appropriatememory cells 79 by corresponding sense amplifier 285 a, as indicated byarrows 81. The sense amplifier 285 a may transfer the received data bitsto a buffer 391 for a first operand, as indicated by arrows 82. Thesecond 8-bit operand (a second operand) for the logical bitwiseoperation may be received by the sense amplifiers 285 a from thecorresponding memory cells. The read data bits are directly transferredto a computing block 393 as indicated by arrows 84.

The computing block 393 may include necessary logics to perform theappropriate logical bitwise operation as instructed by the memorycontroller 100. For example, the computing block 393 may share somelogic units or logic circuitry with the portion of the semiconductormemory device 200 a implementing pop-count operations. The logicalbitwise operation may include any of a number of different logicaloperations such as, for example, AND, OR, NOR, NAND, XOR, and the like.On conclusion of the designated logical bitwise operation between thefirst operand and the second operand, the computing block 393 maygenerate a processing result data, and may provide the processing resultdata to the error correction circuit 400 in FIG. 3. For example, thefirst operand may be a bit vector ‘11010010, whereas the second operandmay be a bit vector ‘10001111’. In case of a logical bitwise ANDoperation between these two bit vectors, the computing block 393 maygenerate the processing result data ‘10000010’ to the error correctioncircuit at arrows 85.

FIG. 17 is a flow chart illustrating a method of operating a memorysystem according to exemplary embodiments.

Referring to FIGS. 2 through 12 and 17, in a method of operating amemory system 20 including a semiconductor memory device 200 a and amemory controller 100 to control the semiconductor memory device 200 a,the semiconductor memory device 200 a receives, from the memorycontroller 100, a write command CMD, an address ADDR and a firstcodeword CW1 including a main data and a first parity data (S310). Thesemiconductor memory device 200 a stores the first codeword CW1 in atarget page designated by the address ADDR, in the memory cell array 300in response to the command CMD (S320).

The semiconductor memory device 200 a determines whether a secondcommand CMD from the memory controller 100 corresponds to an internalprocessing command (S330). When the second command CMD is a read commandinstead of the internal processing command (NO in S330), thesemiconductor memory device 200 a reads the first codeword CW1 from thetarget page (S340) and transmits the first codeword CW1 to the memorycontroller 100 (S345).

When the second command CMD is the internal processing command (YES inS330), the semiconductor memory device 200 a reads the first codewordCW1 from the target page and provides the first codeword CW1 to aninternal processing circuit 390 (S350). The internal processing circuit390 performs an internal processing on the main data of the firstcodeword CW1 to generate a processing result data MD2 and provides theprocessing result data MD2 to the error correction circuit 400 (S360).

The error correction circuit 400 performs an ECC encoding on theprocessing result data MD2 to generate a second parity data and stores asecond codeword CW2 including the processing result data MD2 and thesecond parity data in the target page (S370). The error correctioncircuit 400 selects a same ECC of a plurality of ECCs as an ECC whichthe memory controller 100 uses for generating the first parity data andperforming the ECC encoding using the same ECC. The error correctioncircuit 400 may transmit the second codeword CW2 to the memorycontroller (S380).

FIG. 18 is a cross-sectional view illustrating a package structureincluding the semiconductor memory device according to exemplaryembodiments.

FIG. 18 illustrates a semiconductor package 800 whereby an applicationprocessor 820 and an HBM 830 are die-to-die interconnected.

Referring to FIG. 18, the application processor 820 and the HBM 830 aredirectly connected to each other for example using a through-substratevias (e.g., through-silicon vias) TSVs technology. In this example, apackage on package (PoP) method is not employed wherein the applicationprocessor 820 and the HBM 930 are independently packaged, and then thepackages are repackaged again and connected to each other. Referring toFIG. 18, the application processor 820 is formed on a printed circuitboard (PCB) 810, and then the application processor 820 and the HBM 830are connected to each other through TSV.

The application processor 820 may include a memory controller 821including a first error correction circuit which generates a firstparity data using a first ECC and the HBM 830 may include the internalprocessing circuit and the second error correction circuit disclosedherein. The internal processing circuit and the second error correctioncircuit may be enabled in an internal processing mode and may performabove-mentioned internal processing operation and ECC encoding,respectively.

FIG. 19 is a block diagram illustrating a mobile system including thesemiconductor memory device according to exemplary embodiments.

Referring to FIG. 19, a mobile system 900 may include an applicationprocessor 910, a connectivity unit 920, a user interface 930, anonvolatile memory device 940, a volatile memory device 950 and a powersupply 960. The application processor 910 may include a memorycontroller 911.

The application processor 910 may execute applications, such as a webbrowser, a game application, a video player, etc. The connectivity unit920 may perform wired or wireless communication with an external device.The volatile memory device 950 may store data processed by theapplication processor 910 or operate as a working memory. The volatilememory device 950 may employ the semiconductor memory device 200 of FIG.3.

The nonvolatile memory device 940 may store a boot image for booting themobile system 900. The user interface 930 may include at least one inputdevice, such as a keypad, a touch screen, etc., and at least one outputdevice, such as a speaker, a display device, etc. The power supply 960may supply a power supply voltage to the mobile system 900.

In some embodiments, the mobile system 900 and/or components of themobile device 900 may be packaged in various forms.

The memory controller 911 may include a first error correction circuitwhich generates a first parity data using a first ECC and the volatilememory device 950 may include the internal processing circuit and thesecond error correction circuit disclosed herein. The internalprocessing circuit and the second error correction circuit may beenabled in an internal processing mode and may perform above-mentionedinternal processing operation and ECC encoding, respectively.

Accordingly, the volatile memory device 950 according to exemplaryembodiments may support in-memory processing and may greatly reducetransmission through memory-controller interface. Therefore, exemplaryembodiments may save memory bandwidth and increase usability of thevolatile memory device 950 by generating a second parity data using thesame ECC of the ECCs as the first ECC in the memory controller 911.

Aspects of the present inventive concept may be applied to systems usingsemiconductor memory devices. For example aspects of the presentinventive concept may be applied to systems such as be a mobile phone, asmart phone, a personal digital assistant (PDA), a portable multimediaplayer (PMP), a digital camera, a camcorder, personal computer (PC), aserver computer, a workstation, a laptop computer, a digital TV, aset-top box, a portable game console, a navigation system, or other suchelectronic devices.

The foregoing is illustrative of exemplary embodiments and is not to beconstrued as limiting thereof. Although a few exemplary embodiments havebeen described, those skilled in the art will readily appreciate thatmany modifications are possible in the exemplary embodiments withoutmaterially departing from the novel teachings and advantages of thepresent inventive concept. Accordingly, all such modifications areintended to be included within the present disclosure as defined in theclaims.

What is claimed is:
 1. A semiconductor memory device, comprising: amemory cell array including a plurality of memory cells coupled to aplurality of word-lines and a plurality of bit-lines; a control logiccircuit configured to generate an internal processing mode signaldesignating whether to perform an internal processing operation inresponse to a command received from a memory controller; an internalprocessing circuit configured to output a processing result data byselectively performing the internal processing operation on a first setof data read from the memory cell array, in response to the internalprocessing mode signal, the first set of data including a main data anda first parity data; and an error correction circuit configured togenerate a second parity data by performing an error correction code(ECC) encoding on the processing result data and configured to store theprocessing result data and the second parity data in the memory cellarray, wherein the error correction circuit is configured to generatethe second parity data by selecting the same ECC of a plurality of ECCsas a first ECC which is used for generating the first parity data of thefirst set of data.
 2. The semiconductor memory device of claim 1,wherein the error correction circuit comprises: a plurality of storagedevices configured to store the plurality of ECCs, respectively; and anECC engine connected to the plurality of storage devices, and configuredto generate the second parity data by performing the ECC encoding on theprocessing result data using the same ECC of the plurality of ECCs, inresponse to a control signal from the control logic circuit.
 3. Thesemiconductor memory device of claim 1, wherein the control logiccircuit comprises: a mode register configured to generate the internalprocessing mode signal in response to the command; and a command decoderconfigured to generate a control signal to control the error correctioncircuit by decoding the command.
 4. The semiconductor memory device ofclaim 1, further comprising: an input/output (I/O) gating circuitconnected between the memory cell array and the error correctioncircuit, wherein the I/O gating circuit is configured to change alocation in a target page of the memory cell array, in which the secondparity data is stored, in response to a control signal from the controllogic circuit.
 5. The semiconductor memory device of claim 4, whereinthe I/O gating circuit is configured to store the second parity data ina location corresponding to lower bit addresses of the target page andto store the processing result data in a remaining locationcorresponding to others than the lower bit addresses of the target page,in response to the control signal, and wherein the target page of thememory cell array is configured to store the processing result data andthe second parity data.
 6. The semiconductor memory device of claim 4,wherein the I/O gating circuit is configured to store the second paritydata in a location corresponding to upper bit addresses of the targetpage and to store the processing result data in a remaining locationcorresponding to addresses other than the upper bit addresses of thetarget page, in response to the control signal, and wherein the targetpage of the memory cell array is configured to store the processingresult data and the second parity data.
 7. The semiconductor memorydevice of claim 4, wherein the I/O gating circuit comprises: a cross-barswitch connected to the memory cell array; and a plurality of switchesconnected between the cross-bar switch and the error correction circuit,the plurality of switches configured to transfer the processing resultdata and the second parity data to the cross-bar switch.
 8. Thesemiconductor memory device of claim 1, wherein the error correctioncircuit is configured to transmit the processing result data and thesecond parity data to the memory controller through a data input/outputbuffer.
 9. The semiconductor memory device of claim 1, wherein theinternal processing operation includes a pop-count operation on thefirst set of data stored in a target page of the memory cell array. 10.The semiconductor memory device of claim 1, wherein the internalprocessing operation includes a logical bitwise operation on two sets ofdata stored in at least two target pages of the memory cell array. 11.The semiconductor memory device of claim 10, wherein the logical bitwiseoperation includes one of an OR operation, an AND operation, a NOToperation, a NAND operation, a NOR operation and an XOR operation. 12.The semiconductor memory device of claim 1, further comprising: a pathselection circuit configured to selectively provide the first set ofdata to the internal processing circuit in response to the internalprocessing mode signal.
 13. The semiconductor memory device of claim 1,wherein the semiconductor memory device includes a high bandwidth memory(HBM).
 14. A memory system comprising: at least one semiconductor memorydevice; and a memory controller configured to control the at least onesemiconductor memory device, wherein the memory controller is configuredto generate a first parity data by performing an error correction code(ECC) encoding on a write data using a first ECC and configured totransmit the write data and the first parity data to the at least onesemiconductor memory device, wherein the at least one semiconductormemory device comprises: a memory cell array including a plurality ofmemory cells coupled to a plurality of word-lines and a plurality ofbit-lines, and configured to store the write data and the first paritydata; a control logic circuit configured to generate an internalprocessing mode signal designating whether to perform an internalprocessing operation in response to a command received from the memorycontroller; an internal processing circuit configured to output aprocessing result data by selectively performing the internal processingoperation on a first set of data including the write data and the firstparity data, in response to the internal processing mode signal; and afirst error correction circuit configured to generate a second paritydata by performing an ECC encoding on the processing result data andconfigured to store the processing result data and the second paritydata in the memory cell array, wherein the first error correctioncircuit is configured to generate the second parity data by selectingthe same ECC of a plurality of ECCs as the first ECC which the memorycontroller uses for generating the first parity data.
 15. The memorysystem of claim 14, wherein the memory controller comprises a seconderror correction circuit configured to generate the first parity data byperforming the ECC encoding on the write data.
 16. The memory system ofclaim 14, wherein the memory controller is configured to transmit thefirst parity data to the at least one semiconductor memory devicesimultaneously with the write data.
 17. The memory system of claim 14,wherein the memory controller is configured to transmit the first paritydata to the at least one semiconductor memory device after transmittingthe write data to the at least one semiconductor memory device.
 18. Asemiconductor memory device comprising: a memory cell array including aplurality of memory cells; an error correction circuit configured togenerate a corrected data by performing an error correction on a readdata from the memory cell array, the read data including a first maindata and a first parity data; and an internal processing circuitconfigured to generate a first processed data by performing an internalprocessing on the corrected data including a second main data and asecond parity data, wherein the error correction circuit is furtherconfigured to generate a third parity data by performing an errorcorrection on the first processed data, and store the third parity dataand the first processed data in the memory cell array.
 19. Thesemiconductor memory device of claim 18, wherein the error correctioncircuit is further configured to generate a corrected write data byperforming an error correction on a write data received from a memorycontroller, the write data including a main data and a parity data,wherein the internal processing circuit is further configured togenerate a second processed data by performing an internal processing onthe corrected write data, and wherein the error correction circuit isfurther configured to generate a fourth parity data by performing anerror correction on the second processed data, and store the fourthparity data and the second processed data in the memory cell array. 20.The semiconductor memory device of claim 18, wherein the errorcorrection circuit includes a plurality of storage devices configured tostore an error correction code (ECC), respectively, and is configured toperform the error correction using one of the plurality of storagedevices, and wherein the ECCs comprise at least one of a single errorcorrection (SEC) code, a single error correction and double errordetection (SECDED) code, and double error correction (DEC) code.